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PRELIMINARY TECHNICAL DATA
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Preliminary Technical Data
FEATURES Versatile Analog Signal Conditioning Circuitry On-Board Reference, Crystal Oscillator and Buffers 16-Bit Parallel Buffered Outputs Ideal For DSP and Data Acquisition Card Interfaces Analog and Digital Prototyping Area EVAL-CONTROL BOARD Compatibility PC Software for Control and Data Analysis
Evaluation Board AD766X/AD767X EVAL-AD766XCB/AD767XCB
The EVAL-AD766XCB/AD767XCB is ideal for use with either the Analog Devices EVAL-CONTROL BOARD, or as a stand-alone evaluation board. The design offers the flexibility of applying external control signals and is capable of generating 16-bit conversion results on a parallel buffered outputs. On-board components include an AD780, a +2.5V ultrahigh precision bandgap reference, a signal conditioning circuit with two op-amps and digital logic. The board interfaces with a 96-way connector for the EVAL-CONTROL BOARD, a 20-pin IDC connector for serial output interface, and a 40pin IDC connector for parallel output data. SMB connectors are provided for the low noise analog signal source, an external master clock and an external start/convert input. ORDERING GUIDE
GENERAL DESCRIPTION The EVAL-AD766XCB/AD767XCB is an evaluation board for the AD766X/AD767X 16-bit A/D converter family. The AD766X/AD767X family ( see ordering guide for product list ) is a high speed, successive approximation based architecture with very high performance, low power family of 16-Bit ADCs which operate from a single +5V supply with a 100kSPS to 1MSPS throughput rate range, and a flexible parallel or serial interface. The AD766X/AD767X evaluation board is designed to demonstrate the ADC's performance and to provide an easy to understand interface for a variety of system applications. A full description of the AD766X/AD767X is available in the Analog Devices AD766X/AD767X data sheets and should be consulted when utilizing this evaluation board.
Evaluation board Model EVAL-AD7650CB EVAL-AD7660CB EVAL-AD7662CB EVAL-AD7663CB EVAL-AD7664CB EVAL-AD7665CB EVAL-AD7668CB EVAL-AD7671CB EVAL-AD7675CB EVAL-AD7676CB EVAL-AD7677CB EVAL-CONTROL BRD2
Product AD7650AST AD7660AST AD7662YST AD7663AST AD7664AST AD7665AST AD7668YST AD7671AST AD7675AST AD7676AST AD7677AST Controller Board
FUNCTIONAL BLOCK DIAGRAM
+/-5 V CNVST REF 2.5V AD780 REF CNVST +/-12 V +5 V VL
AUX_IN SIGNAL CONDITIONING
AD766x or AD767x
IN
BUSY
DIGITAL LOGIC DATA
40 PIN CONN
96 PIN CONN
IN MCLK
20 PIN CONN
Configuration switches MCLK
Clock
REV. PrK
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
OPERATING THE EVAL-AD766XCB/AD767XCB The EVAL-AD766XCB/AD767XCB is a four-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the AD766X/AD767X. Figure 1 shows the schematics of the evaluation board. The layouts of the board are given in : Top side silk-screen - Figure 2 Top side layer - Figure 3 Ground layer - Figure 4 Shield layer - Figure 5 Bottom side layer - Figure 6 Bottom side silk-screen - Figure 7. The EVAL-AD766XCB/AD767XCB is a flexible design that enables the user to choose among many different board configurations. A description of each selectable jumper/switch is listed in Table II and the available test points are listed in Table III. Note that the button of a switch in position A ( U3 side ) defines a low level. The EVAL-AD766XCB/AD767XCB is configured in factory with 0 to 2.5 V ADC input range for the AD7660, AD7664, and AD7675/7676/7677 and +/-5V for the AD7663/7665/ 7671; front-end amplifiers U6 and U7 set with a gain of +1, powered through the EVAL-CONTROL BOARD, and the on-board CNVST generation used. On-board or external CNVST could be used. When an external CNVST signal is applied, this signal should have very low jitter and sharp edges to get the best noise performance of the part. Meanwhile, it is recommended to use the on-board CNVST generation which is done by dividing MCLK signal (20MHZ) by the numbers shown in Table I, which are entered in the software. Activity on BUSY pin of the ADC turns on the LED. Table I. CNVST GENERATION tor P1. When slave serial reading mode of the AD766X/AD767X is used, the external serial clock SCLK applied to the ADC is at half the MCLK frequency. Power Supplies and Grounding The evaluation board ground plane is separated into two sections: a plane for the digital interface circuitry and an analog plane for the analog input and external reference circuitry. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths. The EVAL-AD766XCB/AD767XCB has three power supply blocks: a single 5V supply VA (SJ1) for the AD766X/AD767X and the reference voltage circuitry, a digital 5V supply VL (SJ2) for the digital interface circuitry and the digital section of the ADC, and a selectable +/-12V (with a possibility of +/-15V with control Brd2) or +/-5V supply for the analog signal conditioning circuitry (SJ3). All supplies are decoupled to ground with 10 F tantalum and 0.1 F ceramic capacitors. Analog Input Ranges The analog front-end amplifier circuitry U6 and U7 allows flexible configuration changes such as positive or negative gain, input range scaling, filtering, addition of a DC component, use of different op-amp and supplies. Figure 1 shows the front end op-amp configuration used with the AD7660/7663/7664/7665/7671/7675/7676/7677. In some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10V, 5V, 2.5V, or 0 to +5V. For the AD76XX parts which do not have directly those input ranges like the AD7660/7664/7675/7676/7677, by simple modifications of the input driver circuitry of the EVAL-AD766XCB/AD767XCB, bipolar and wider input ranges can be used without any performance degradation. Components values required and resulting full-scale ranges are shown in table IV and table V. In factory, the analog input of U6 is set at mid-scale (R6=R7=590 ) for the AD7660/7664/7675/7676/7677. For AD7663/7665/7671, R7 is not connected to maintain the input at 0V (mid-scale). This allows a transition noise test without any other equipment. An FFT test can be done by applying a very low distortion AC source. EVAL-CONTROL BOARD INTERFACE The EVAL-AD766XCB/AD767XCB interfaces to the EVALCONTROL BRD2 through the 96-way connector. RUNNING THE EVAL-AD766X/AD767XCB SOFTWARE Software Description The EVAL-AD766XCB/AD767XCB comes with software for analyzing the AD766X/AD767X. Through the EVAL-CONTROL BRD2 one can perform a histogram to determine code transition noise, and Fast Fourier Transforms (FFT's) to determine the Signal-to-Noise Ratio (SNR), Signal-to-Noiseplus-Distortion (SNRD) and Total-Harmonic-Distortion (THD). The front-end PC software has four screens as shown in Figure 8,9,10 and 11. Figure 8 is the Setup Screen where input voltage range, sample rate, number of samples are selected. Figure 9 is the Histogram Screen, which allows the code distribution for DC input and computes the mean REV. PrK - 2 -and standard deviation.
Part AD7660 AD7662/68 AD7663 AD7664/50 AD7665 AD7671 AD7675 AD7676 AD7677
Division Factor 200 40 80 35 35 20 200 35 20
Throughput Rate 100KSPS 500KSPS 250KSPS 571KSPS 571KSPS 1MSPS 100KSPS 571KSPS 1MSPS
Conversion data is available at the output bus BD on U3, on the 40-pin connector P2, and on the 96-pin connector P3. Additionally, BD data is updated on the falling/rising edge of DBUSY and BBUSY on P3, low when BD data is valid are delayed from the BD data by about 20 ns to ease the interface. When either parallel or serial reading mode of the ADC is used, the data is available on this parallel bus. When serial reading mode of the ADC is used, the serial interface signals of the ADC are buffered and available on the 20-pin connec-
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
Figure 10 is the FFT Screen, which performs an FFT on the captured data, computes the Signal-to-Noise Ratio (SNR), Signal-to-Noise-plus-Distortion (SINAD) and total-Harmonic-Distortion (THD). Figure 11 is the time domain representation of the output. When the on-board CNVST generation is used, a synchronous FFT could be achieved by synchronizing the external AC generator with the Fsync signal (TP11) which is an exact division by 2 of MCLK. Software Installation - Double-Click on Setup.exe from the CD-ROM and follow the installation instructions. NOTE: The software runs under Windows 95/98 only.
TABLE II. JUMPER DESCRIPTION Jumper Default position Designation with the control board ( Factory settings) Function
JP1
A
Selection of the positive supply of the front-end amplifier U6. When JP1 is in position A, the +12V supply from the control board is applied to JP3 otherwise VS+ on SJ3 is used. Selection of the negative supply of the front-end amplifier U6. When JP2 is in position A, the -12V supply from the control board is applied to JP4 otherwise VS- on SJ3 is used. Selection of the positive supply of the front-end amplifier U6. When JP3 is in position A, the +5V supply from the control board is used otherwise JP1 output is used. Selection of the negative supply of the front-end amplifier U6. When JP4 is in position A, the -5V supply from the control board is used otherwise JP2 output is used. Selection of the master clock MCLK signal. When JP5 is in position A, the signal on J4 is used otherwise the on-board 20 MHz clock is used as a MCLK signal. MCLK signal is used to generate the on-board CNVST signal and the external serial clock SCLK. Selection of RDC ( Read during convert ). When the button of the switch is close to J4 connector ( not A position ) and when the serial reading mode is selected, the data are read during conversion otherwise the data are read after conversion. JP6 has no use in parallel reading mode. Selection of PD ( Powerdown ). When the button of the switch is close to J4 connector ( not A position ), the ADC is in power-down mode. Spare switch. Selection of RESET. When the button of the switch is close to J4 connector ( not A position ), the ADC is reset. Selection of SER/PAR ( serial/parallel reading mode ). When the button of the switch is close to J4 connector ( not A position ), the data are read in serial mode otherwise the data are read in parallel mode. Selection of OC/2C ( coding ). When the button of the switch is close to J4 connector ( not A position ), the ADC uses a straight binary coding otherwise the twos complement coding is used. Selection of WARP. When the button of the switch is close to J4 connector ( not A position ), the ADC uses the WARP mode which is the fastest one. With the AD7660, JP12 is a spare switch. -3-
JP2
A
JP3
A
JP4
A
JP5
not A
JP6
A, U3 side
JP7
A, U3 side
JP8 JP9
A, U3 side A, U3 side
JP10
A, U3 side
JP11
not A, SJ4 side
JP12
A, U3 side
REV PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
TABLE II. JUMPER DESCRIPTION Jumper Default position Designation with the control board ( Factory settings) Function
JP13
A, U3 side
Selection of IMPULSE. When the button of the switch is close to J4 connector ( not A position ), the ADC uses the IMPULSE mode which is the mode with the lowest power dissipation. With the AD7660, JP13 is a spare switch. TEST1. For factory use only and it is pull down. TEST0. For factory use only and it is pull down. Selection of EXT/INT ( use of external or internal serial clock ). When the button of the switch is close to J4 connector ( not A position ) and when the serial reading mode is selected, the data are read with an external serial clock SCLK generated from the master clock MCLK otherwise the data are read with the ADC serial clock. When external serial clock reading mode is selected, MCLK has to be fast enough to be able the read the data properly as explained in the AD766X data sheet. JP16 has no use in parallel reading mode. Selection of INVSYNC ( SYNC active level ). When the button of the switch is close to J4 connector ( not A position ) and when the master serial reading mode is se lected, the SYNC signal is active Low. JP17 has no use in parallel reading mode or slave serial reading mode. Selection of INVSCLK ( SCLK active edge ). When the button of the switch is close to J4 connector ( not A position ) and when the serial reading mode is selected, INVSCLK is high. JP18 has no use in parallel reading mode. Selection of CNVST signal. When JP19 is in position A, the signal on J3 is used otherwise the on-board CNVST generation is used. MCLK signal is used to generate the on-board CNVST signal. Selection of REF signal. When JP20 is in position A, the REF is buffered. When JP20 is not in position A, the REF is not buffered.
JP14 JP15 JP16
A, U3 side A, U3 side A, U3 side
JP17
A, U3 side
JP18
A, U3 side
JP19
not A
JP20
not A
Table III. EVAL-AD766XCB/AD767XCB Test Points Test Point Available Signal
Table IV. Component values Vs. Input ranges ( AD7660 ) Input range 10V 5V 0 to -5V R1 8k 8k 8k R3 1k 2k 8k R6 8k 6.67k 0 R7 10k 10k none
TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16
DGND DGND SIG+ AGND REF BUSY RD CS AGND CNVST FSYNC OVDD DVDD VANA1 AGND SIG-
Digital ground Digital ground ADC Analog input Analog ground close to SIG+ ADC Reference input ADC BUSY signal ADC RD signal ADC CS signal Analog ground close to REF ADC CNVST signal MCLK divided by 2 ADC digital output supply ADC digital core supply ADC analog supply Analog ground close to SIGADC Analog input
Table V. Component values Vs. Input ranges ( AD7664 ) Input range 10V 5V 0 to -5V R1 2k 2k 1k R3 250 500 1k R6 8k 6.67k 0 R7 10k 10k none
-4-
REV. PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
TESTING METHODS Histogram
USE OF EVAL-AD766XCB/AD767XCB AS STANDALONE EVALUATION BOARD
To perform a histogram test, apply a DC signal to the input. It You have the option of using the is advised to filter the signal to make the DC Source noise com- EVAL-AD766XCB/AD767XCB as a stand-alone evaluation patible with that of the ADC. C26 provides this filtering. board. This method does not require the control board, nor does it require use of the accompanied software. The digital output AC Testing will now be available on P1 (20-pin connector, for use in serial To perform an AC test, apply a sinusoidal signal to the mode) or P2 (40-pin connector, for use in parallel mode). Cerevaluation board. Low distortion, better than 100dB, is required tain modifications have to be made on the board to allow proper to allow true evaluation of the part. One possibility is to filter the operation of the evaluation board. Refer to Table II to obtain input signal from the AC source. There is no suggested the jumper positions for stand-alone operation. When in standbandpass filter but consideration should be taken in the choice. alone, CNVST could be externally applied or is generated Furthermore, when the full-scale input range is more than a few internally according to Table I. Vpp, it is recommended that you use the on board amplifier to amplify the signal, thus preventing the filter from distorting the Please refer to Figure 1 to obtain the data output pins on the input signal. connectors. Please refer to Figures 8,9,10 and 11 to see the screens of the software. Data is updated on the falling edge of BUSY. BCS and BWR are inputs to the FPGA and are connected to P1 and P2. When BCS, CONTROL are low and BWR is high, which is the default value defined by the on-board pull-up/pull-down resistors, the data bus BD available on the P2 connector is enabled. SUPPLYING THE BOARD FOR STAND-ALONE USE SJ1 is the analog supply. Connect VA+ to +5V and AGND to GND. SJ2 is the digital supply. SJ2 requires the same values as SJ1, and SJ2 may be connected to SJ1. SJ3 is the supply for the front end amplifier (U6). Connect +12V to VS+, GND to AGND, and -12V to VS-.
Software Description The AD16bit.exe is the software which allows you to analyze different performance characteristics of the AD766X, AD767X, AD97X and AD67X 16-bit ADC family. The software allows you to test the histogram as well as perform different AC tests. Setup Requirements - Evaluation Control Board 2 (ADSP2189) - Evaluation Board - Power Supply (AC 15V/1A source could be bought from ADI) - Parallel Port Cable (provided with the evaluation control board) - AC Source (low distortion) - DC Source (low noise) - Bandpass Filter (value based on your signal frequency, low distortion)
REV PrK
-5-
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
EVAL-BOARD SETTING FOR INPUT CONFIGURATIONS The AD7663/AD7665 and AD7671 have the ability to operate both unipolar and bipolar range. The available options are +/- 10V, +/- 5V, +/- 2.5V, 0 to 10V, 0 to 5V and 0 to 2.5V. Table VI shows the required configurations for each input range. (REF = 2.5V). Table VII lists the default settings of the board for all parts.
Table VI. AD7663/7665/7671 Analog Input Configuration
Input Voltage Range 4 REF 2 REF REF 0 V to 4REF 0 V to 2REF 0 V to REF IND(4R) VIN VIN VIN VIN VIN VIN INC(4R) INGND VIN VIN VIN VIN VIN INB(2R) INGND INGND VIN INGND VIN VIN INA(R) REF REF REF INGND INGND VIN
Table VII. Default Settings
Component/Part R7 S9 S10 R48 C40 R47 C39
AD7660 AD7663 AD7664 AD7665 AD7671 AD7675 AD7676 AD7677
590 None 590 None None 590 590 590
None None None None None 0 0 0
0 0 0 0 0
None None None
0 0 15 0 0 15 15 15
None None 2.7nF None None 2.7nF 2.7nF 2.7nF 15 15 15 2.7nF 2.7nF 2.7nF
-6-
REV PrK
8
2
+VIN
VOUT 4 8
TEMP 2 18 19
GND
1
20
4
AVDD
OVDD
DVDD
AGND
DGND
DGND
C28 .1uF JP20
C29 .1uF
A
REF TP5
REF 37
17
8
7
1
4
R44 C13 S3
V+ V+
INB1 INB2 INBN T0 T1
S5
S7
S20
S8
GND
C38 C37 .1uF S17
GND GND
S10
R43 R42 0.0 U7
8 7 2 6 3 SIG-
C36
S9
GND
PRELIMINARY TECHNICAL DATA
TP16 SIGR45 0.0 R47 15
C39
34 4 33 7 6 5 8 30 36
PD BYTESWAP RESET IMPULSE WARP OB/2C SER/PAR T1/PDREF T0/E0C
1
4
REV PrK
V+ VANA2
S18 1
SIG_2.5V
S19 R67 U2A 0.0
GND
R66 U2B
GND 6 1 5 + DVDD OVDD 3 VANA 2
VANA2
C1 .1uf
VANA2
C27
VANA2 GND GND 7 GND +
C25 .1uF 10uF OVDD TP12 DVDD TP13 R34 0.0
C33
VANA TP14
AD780BR
6
1uF U5
GND
VOUT
C9B .1uF
C10 C9T 10uF
GND
7 1 N/C N/C
2.5/3vSEL
AD8032AR
C30 .1uF
GND
3 TRIM
5
R8 1 Meg U1
D[0..15]
GND V+
VR1 50K C5 10uF C20 .1uF
D[0..15]
REF
S16
GND GND
C31T TP9 AGND 1uF 47uF
C31B
C32B
R2 C19 R3 0.0 U6
GND 2 6 3 5 SIG+ SIG_2.5V
GND
38
TP3 SIG+ S12
REFGND
J1 AIN+
R1
S13
TP4 AGND AD8021 R46 R48 15 S1 S15 S2 S4 S6 S14 0.0 S11
R5
0.0
AD766X
D0 D1 D2/DIVSCLK(0) D3/DIVSCLK(1) D4/EXT/INT D5/INVSYNC D6/INVSCLK D7/RDC/SDIN D8/SDOUT D9/SCLK D10/SYNC D11/RDERROR D12 D13 D14 D15 CNVST BUSY
9 10 11 12 13 14 15 16 21 22 23 24 25 26 27 28 35 29
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
CNVST BUSY
Figure 1. Schematic
C26
V-
-7-
R7 590 R70 C40
GND
GND
R6 590
C22 .1uF
C34 10pF
IN_D IN_C IN_B IN_A INGND
43 42 41 40 39
IN_D/IN+ IN_C/REFA IN_B/INA1 IN_A INGND/IN-
A0 RD CS
3 31 32
A0 RD CS
SIG_2.5V
INB1 INB2 INBN
46 44 45 47 48
T0/EOC T1/PDREF SER/PAR OB/2C WARP IMPULSE RESET BYTE PD T1 T0
J2 AIN-
R59
TP15 AGND
5
R61 AD8021
V-
0.0
GND
R60 590 R71 C42 .1uF
R29 590
C41
V-
C35 10pF Drawn By: M.M Date: Appr. By:
GND
A.G Rev# D Sheet 2
Date: Size of Printing Date: 4-Oct-2001 3
AD766X Evaluation Board
SIG_2.5V
EVAL-AD766XCB/AD767XCB
B
VDIG VDIG CNVOUT
C11 .1uF U8 TP10
D[0..15] DATA CS DCLK 89 DCLK DCLK OE 2 3 STATUS 4 CONF_DONE 86 DATA DATA 1 D[0..15]
C12 .1uF EPC1441 1K R23 R62 1K 10K R32 1K R58
GND CONFIG BWR
C15 .1uF
C16 .1uF
C17 .1uF
C18 .1uF
C7 .1uF
10K R40
10K R10
R31 1 Meg U3 JP19
CNVST
'$%
DATA
DCLK
+5v
VANA2
CNVSTIN J3
A
R10A 100 P2 TP8 TP7 R10B 100
P3A
VANA2
SJ1
L1
VA+ AGND
1 2
$ #
GND
TP6 BUSY
EVAL-AD766XCB/AD767XCB
C2 10uF EPF6010T(100)
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D9
GND
GND
GND CNVST CNVOUT DVDD
BUSY RD CS CNVST
VDIG
OVDD
R41 49.9
DVDD
SJ2 L2
CONTROL ADCOK BRD
OVDD
VL
BWR
AD1 AD0 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 DBUSY
DGND
C8 10uF C7T R64
T0/EOC GND T1/PDREF T0
1 2
L3
SDOUT SYNC SCLK BD15 BD14 BD13 BD12 BD11 BD10 BD9 BD8 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 AD1 AD0 +5V BCS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND +12V 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
BYTE RESET WARP OB/2C SER/PAR IMPULSE
C4 10uF C5B .1uF 0.0
PD A0
C6 10uF C7B .1uF
C5T
BYTE RESET WARP OB/2C SER/PAR IMPULSE TEST1_OUT T0 PD
27 26 25 24 17 16 15 14 11 10 9 8 2 1 100 99 13 98 96 95 90 91 32 94 30 31 28 29 97 92 93 33 12 34 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SCLKIN BUSY RD CS CNVST CNVSTOUT BYTE RESET WARP OB/2C SER/PAR IMPULSE TEST1_OUT TEST0 PD A0 EOC PDREF -5V
R65 R63 0.0
P1
DATA DCLK
VDIG
VDIG -12V
C5 C6 C7 C19 C18 B18 A18 B17 B15 B14 B13 B11 B10 B9 B7 B6 B5 B3 B2 A14 C15 A32 B32 C32 A31 B31 C31 C30 A8 B8 C8 A30 41 40 82 80 79 78 77 76 75 74 73 66 61 60 59 58 51 50 83 84 49 65 64 63 48 62 47 46 44 43 42 35 39 BBUSY DSEL SCNVST SCLK SYNC SDOUT SDIN MCLK
STATUS
PD
BYTE
RESET
IMPULSE
WARP
OB/2C
SER/PAR
TEST1_OUT
T0
D4
D5
D6
10K
10K
10K
10K
10K
100
10K
10K
10K
10K
MCLK
-12V
-5V
10K
10K
10K
A
JP4
GND
D7
R13
R11
R17
R14
R15
R12
R16
R18
R19
R20 R21
R22
R35
T1
TEST0_IN
EXT/INT
INVSYNC
INVSCLK
RDC
PRELIMINARY TECHNICAL DATA
TEST0_IN
TEST1_OUT
JP12
JP11
JP10
JP14
JP15
JP16
JP17
JP18
JP7
JP8
JP9 JP13
JP6
Figure 1 Schematic
VVV+ V+ CONF_DONE CONFIG CE MSEL 72 36 CONF_DONE CONFIG 4 22 GND
-8-
C23 10uF C21 10uF
+12V
+5V
A
JP3
AD1 AD0 BD0 BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 DBUSY CONTROL ADCOK BWR BRD BCS BBUSY DSEL SCNVST SCLK SYNC SDOUT SDIN MCLK STATUS SYNC SCLK
P3B
JP1
A
SJ3
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
L4
BCS BBUSY BRD BWR DSEL CONTROL
L5
10K R24 J5 FSYNC R36 1K
GND SCNVST SDIN D3 GND
VS+ AGND VS-
1 2 3
10K R26 10K R27 R28 D1
ADCOK A K BCS
GND
A
JP2
10K 357 R30 10K R33
A
U4
3 OUT +5v
VDIG 4
JP5 J4 20MHz osc
VDIG 1 GND 2
P3C C3 .1uF
T1 VDIG
R37 10K
R38 10K
R23A 10K
R23B TP1 10K DGND TP2 DGND
A23 A24 A25 A26 A29 B21 B22 B23 B24 B25 GND
C10 C17 A9 C9 A17 B1 A4 A12 A16 A20 B4 B12 B16 B20 C4 C12 C16 C20 B26 B27 B28 B29 B30 C21 C22 C23 C24 C25 C26 C29 A21 A22
Drawn By: M.M Appr. By: A.G Rev# D 2
Date: Date: Size of 3 Printing Date: 28-Sep-2001 AD766x Evaluation Board
GND
B
REV. PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
Figure 2. Top side silk-screen ( Not to Scale ).
Figure 3. Top side ( Not to Scale ).
REV PrK
-9-
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
Figure 4. Ground Layer ( Not to Scale ).
Figure 5. Shield Layer ( Not to Scale ).
-10-
REV. PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
Figure 6. Bottom side layer ( Not to Scale ).
Figure 7. Bottom side silk-screen ( Not to Scale ).
REV PrK
-11-
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
2) The part under evaluation is chosen from this menu. The available choices are AD766X, AD97x and AD67x.
1) The Run button starts the software. All input configurations are read by the software after running the software. You will need to press this button first.
3) Input Configurations are chosen here. For the AD766X/ AD767X, the available choices are: PwDown, Reset, Interface, Coding, Byte, and Reading.
4) The choice of test is made here. You may choose to perform either a Histogram test or an AC test.
Figure 8. Setup Screen
This is the performance window. 5) You may choose to take one sample (Sample,F3), or perform continuous sampling (Continuous,F4). You may also choose the Help, Save, Print or Quit options. The Help menu will show you a description of the functionality of the chosen command.
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REV. PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
The results are displayed on this chart. You may also use the cursor (yellow) and drag it to your desired location, where the X-axis value and the Y-axis value will be displayed.
Figure 9. Histogram Screen
This control allows you the choice of display. You have the option of Time or Histogram. You also have the option of changing the X-axis unit
Different measurements are displayed here. The DC value, transition noise, and other values.
REV PrK
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PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
The results are displayed on this chart. You may also use the cursor (yellow) and drag it to your desired location, where the X-axis value and the Y-axis value will be displayed.
Figure 10. FFT Screen
This is the control that allows you the choice of either time domain or frequency domain. You may also change the X-axis unit here. AC test results are shown here. You also have the choice of viewing the amplitude of a certain FFT component by changing the FFT component menu. You may choose either a Kaiser window or a Blackmann-Harris window or a Sync FFT from this menu. . When choosing a Sync FFT, you will need to synchronize your analog source to the sampling frequency. The input frequency should be the value Sync Fr, which is to the right of Target frequency. The process for this is as follows: 1. You Choose a Target frequency 2. The software calculates an integer n based on the target frequency you entered and the sampling frequency, Fsamp. 3. The software rounds up the value n to the next prime number. 4. The software then calculates the corresponding input frequency (Fin) and displays that as Sync Fr. The equation, (capture window size) is shown below: (1/Fsamp) * (number of samples) = n * (1/Fin)
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REV. PrK
PRELIMINARY TECHNICAL DATA EVAL-AD766XCB/AD767XCB
You can also view the output in the Time domain as shown below.
Figure 11. Time-Domain Screen
To view the Time domain, select Time in this menu.
REV PrK
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